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Based on this objective function, a design that can solve puzzles with high orders in a short period of time will have a much higher chance of winning than designs that are only able to solve puzzles of small orders. Therefore, you are encouraged to design an FPGA solver that is able to deal with puzzles with as high an order as possible. As a reference, most existing software Sudoku solvers are able to solve puzzles with orders up to N=7 within minutes.
Subsequently, the values of each cell of the puzzle will be transmitted in a row-major fashion, starting from the top-left, going down to bottom-right. A cell value of 0 indicates that a cell is empty. Otherwise, the given value of a cell is transmitted.
For example, the first puzzle shown in the Background page would be transmitted as:
The RS-232 connection should be set to a baud rate of 115200 bps, 8-bit data, no parity bit and 1 stop bit (115200 8N1).
For example, the solution to the puzzle shown above will be transmitted as:
In other words, the value of the checksum is the sum of the values of all the cells with r + c added to an even number, minus the sum of the values of all the cells with r + c added to an odd number. Another way to look at it is that the sign of the first cell of a row is always the opposite of the first cell of the previous row. All subsequent cells in the same row will then be added to the checksum with alternating signs.
Only the lower 8 bits of the checksum are transmitted.
For example, the checksums for the sample puzzles shown in the Background page can be calculated as:
- 1 + 4 - 5 + 2 + 9
- 3 - 9 - 4 + 5 - 1
+ 5 + 8 - 6 + 7
+ 3 - 7
+ 6 - 2 - 5 + 1
- 3 + 4
+ 4 - 3 + 6 + 2
- 8 + 2 - 7 - 4 - 5
+ 1 + 5 - 2 + 8 - 4
The following is the list of currently approved systems:
Note that in order to facilitate our evaluation process, you need to submit together with your design the result of solving benchmark puzzles posted in this website using your solver. See Design Submission for details.
The time to solve a puzzle is defined as the time commencing with the transmission of the checksum byte at the end of the data input transmission and finishing with the receipt of the checksum byte at the start of the data output transmission. Therefore, the delay of the serial connection will not affect the timing significantly.
Sample puzzles and controlling software that will run on the host PC, will be posted in the Benchmarks page as soon as they are ready.